/*===============================================
Copyright (c): Technology Co.,Ltd. ALL rights reserved. 
                                                                 
  Create by: L
      Email:
       Date: 2023/07/05
   Filename:
Description:
    Version:
Last Change:
                                                                 
=======================================*/
                                                                 
`ifndef MII_IF_SV
`define MII_IF_SV

interface mii_if #(parameter PORT_NUM = 4)(input logic clk, input logic rst_n);
	/*Simple MII Interface*/
	logic	[PORT_NUM - 1 : 0]		mii_rx_clk;
	logic	[PORT_NUM - 1 : 0]		mii_rx_dv;
	logic	[PORT_NUM - 1 : 0][3:0]	mii_rx_data;
	logic	[PORT_NUM - 1 : 0]		mii_tx_clk;
	logic	[PORT_NUM - 1 : 0]		mii_tx_en;
	logic	[PORT_NUM - 1 : 0][3:0]	mii_tx_data;
	
	logic	[PORT_NUM - 1 : 0]		mii_tx_err;
	logic	[PORT_NUM - 1 : 0]		mii_rx_err;
	
	clocking drv_clk @(posedge mii_tx_clk);
		default input #1 output #1;
		output mii_tx_en;
		output mii_tx_data;
	endclocking

	clocking mon_clk @(posedge mii_rx_clk);
		default input #2 output #1;
		input mii_tx_en;
		input mii_tx_data;
		input mii_rx_dv;
		input mii_rx_data;
	endclocking
	
endinterface

interface test_if #(parameter PORT_NUM = 4)(input logic clk, input logic rst_n);
	logic	[PORT_NUM - 1 : 0][15:0]	drop_num;

	clocking mon_clk @(posedge clk);
		default input #2 output #1;
		input drop_num;
	endclocking
endinterface

`endif
